Sigma-Delta Analog-to-Digital Converters (ADC) are known to receive an analog input signal, sample it by a 1-bit Sigma-Delta modulator at a sampling rate, and pass the sampled signals through a decimation filter to obtain a digital signal. As is also known, the decimation filter includes an integrator, a sample and hold circuit, and a differentiator. The integrator is operably coupled to receive the sampled analog signals at a rate that is a multiple of the sampling rate. For example, the integrator's clock rate may be 64, 128, or 256 times the sampling rate of the 1-bit Sigma-Delta modulator. As the integrator receives the sampled signals, it integrates them. The sample and hold circuit receives the integrated signals, samples and holds them at a rate corresponding to a data word rate. The differentiator is operably coupled to receive signals outputted by the sample and hold circuit and differentiates them at the data word rate.
By including the decimation filter in the ADC, noise is reduced in lower frequency range (i.e., the range of interest for audio equipment) and effectively shifted to higher frequencies. A low pass filter is then used to attenuate the noise in the higher frequencies. The amount of noise reduction in the lower frequency range is dependent on the order of the decimation filter and the sampling rate. As the order of the decimation filter increases, the noise in the lower frequency range decreases, but the noise in the higher frequencies is greater. The noise is also reduced in the lower frequency range by increasing the sampling rate of the Sigma-Delta modulator. Thus, a balance between the sampling rate and order of the decimation filter may be obtained to produce the desired noise rejection.
If the decimation filter is a second order filter, it is inherently stable, which simplifies the compensation circuitry in comparison to higher order filters. A second order decimation filter, however, may saturate at the positive or negative rail when it is filtering a maximum positive or negative value. If the filter saturates, the resulting output is corrupted, which would cause audible errors in most audio equipment. To overcome the saturation problem, a decimation filter may include saturation logic. The saturation logic includes a saturation detection module and a saturation correction module. The saturation detection module is operably coupled to the input of the differentiator, while the saturation correction module is coupled to the output of the differentiator. If the saturation detection module detects a saturation condition, it sets a saturation bit, The saturation correction module interprets the saturation bit and it corrects the output when the bit is set. For example, when the decimation filter processes data as two's complement data, the maximum negative value is a bit difference than the maximum positive value, with respect to the binary numbering system (e.g., 1000 represents -8, while 0111 represents +7, for a four bit system).
While the above saturation detection and correction modules correct an overflow condition, they require a relatively large amount of circuitry to implement, in the order of 1 gate per bit of the digital word. As is known, the more gates a circuit requires, the more die area it requires, thus increasing the cost of manufacture, and the sales price of an Analog to Digital Converter.
Therefore, a need exists for a method and apparatus that provides overflow detection in decimation filters with a minimal number of extra gates.